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ps022901-0508 product specification z86e33/733/e34 z86e43/743/e44 cmos z8 ? otp microcontrollers copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com
ps022901-0508 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology describe d is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crim zon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
ps022901-0508 revision history cmos z8 ? otp microcontrollers product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page no may 2008 01 original issue. all
ps022901-0508 table of contents cmos z8 ? otp microcontrollers product specification iv table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 handshake timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 eprom programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 application precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ps022901-0508 architectural overview cmos z8 ? otp microcontrollers product specification 1 architectural overview zilog?s z86e33/733/e34, e43/743/e44 8-bit one-time programmable (otp) microcon- trollers are members of zilog?s single-chip z8 ? mcu family featuring enhanced wake-up circuitry, programmable watchdog timers, lo w noise emi options, and easy hardware/ software system expansion capability. four basic address spaces support a wide range of memory configurations. the designer has access to three additional control registers that allow easy access to register mapped peripheral and i/o circuits. for applications demanding powerful i/o capa bilities, the z86e33/733/ e34 have 24 pins, and the z86e43/743/e44 have 32 pins of dedicated input and output. these lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and parallel i/o with or without handshake, and address/ data bus for interfaci ng external memory. all signals with an overline are active low. for example, b/w , for which word is active low, and b /w, for which byte is active low. power connections follow th ese conventional descriptions: features table 1 lists the features of z86e33/733/e34, e43/743/e44. connection circuit device power v cc v dd ground gnd v ss table 1. z86e33/733/e34, e43/743/e44 features device rom (kb) ram 1 (bytes) i/o lines speed (mhz) z86e33 4 237 24 12 z86733 8 237 24 12 z86e34 16 237 24 12 z86e43 4 236 32 12 z86743 8 236 32 12 note:
ps022901-0508 architectural overview cmos z8 ? otp microcontrollers product specification 2 ? standard temperature (v cc = 3.5 v to 5.5 v) ? extended temperature (v cc = 3.5 v to 5.5 v) ? available packages: ? 28-pin dip/soic/plcc otp (e33/733/e34) ? 40-pin dip otp (e43/743/e44) ? 44-pin plcc/lqfp otp (e43/743/e44) ? software enabled watchdog timer (wdt) ? push-pull/open-drain programmable on port 0, port 1, and port 2 ? 24/32 input/output lines ? clock-free wdt reset ? auto power-on reset (por) ? programmable otp options: ? rc oscillator ? eprom protect ? auto latch disable ? permanently enabled wdt ? crystal oscillator feedback resistor disable ? ram protect ? low-power consumption: 60 mw ? fast instruction pointer: 0.75 s ? two standby modes: stop and halt ? digital inputs cmos levels, schmitt-triggered ? software programmable low emi mode ? two programmable 8-bit counter/timers ea ch with a 6-bit pr ogrammable prescaler ? six vectored, priority interrupt s from six different sources ? two comparators z86e44 16 236 32 12 1 general-purpose table 1. z86e33/733/e34, e43/743/e44 features (continued) device rom (kb) ram 1 (bytes) i/o lines speed (mhz)
ps022901-0508 architectural overview cmos z8 ? otp microcontrollers product specification 3 ? on-chip oscillator that accepts a crystal, ce ramic resonator, lc, rc, or external clock drive functional block diagram figure 1 displays the functional block diagram. figure 1. functional block diagram two analog comparators interrupt control port 3 counter/ otp program counter timers (2) machine timing & inst. alu control flags register pointer register file port 2 port 0 i/o (bit programmable) address or i/o input v cc gnd xtal output (nibble programmable) 4 4 8 port 1 address/data or i/o (byte programmable) ((e43/743/e44 only) reset wdt, por as ds r/w reset (e43/743/e44 only)
ps022901-0508 architectural overview cmos z8 ? otp microcontrollers product specification 4 figure 2. eprom programming block diagram address counter clr (p00) clk (p01) ad 13-0 z8 mcu pgm + test mode logic epm p32 pgm p02 ce xt1 v pp p33 oe p31 z8 port 2 data mux d7-0 ad 11-0 ad 11-0 d7-0 d7-0 eprom test rom otp options address mux
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 5 pin description figure 3. 40-pin dip pin configuration standard mode table 2. 40-pin dip pin identification standard mode pin no symbol function direction 1r/w read/write output 2-4 p25-p27 port 2, pins 5,6,7 input/output 5-7 p04-p06 port 0, pins 4,5,6 input/output 8-9 p14-p15 port 1, pins 4,5 input/output 10 p07 port 0, pin 7 input/output 11 v cc power supply 12-13 p16-p17 port 1, pins 6,7 input/output 14 xtal2 crystal oscillator output p00 p33 p24 p25 p26 p27 xtal2 xtal1 p32 p23 p22 p21 p20 p02 p01 v cc p04 p03 p30 p36 p37 p35 p34 p05 p06 p14 p15 p07 p16 p17 p31 r/w as ds p12 gnd p11 p10 reset p13 1 dip 40?pin 20 40 21
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 6 15 xtal1 crystal oscillator input 16-18 p31-p33 port 3, pins 1,2,3 input 19 p34 port 3, pin 4 output 20 as address strobe output 21 reset reset input 22 p35 port 3, pin 5 output 23 p37 port 3, pin 7 output 24 p36 port 3, pin 6 output 25 p30 port 3, pin 0 input 26-27 p00-p01 port 0, pins 0,1 input/output 28-29 p10-p11 port 1, pins 0,1 input/output 30 p02 port 0, pin 2 input/output 31 gnd ground 32-33 p12-p13 port 1, pins 2,3 input/output 34 p03 port 0, pin 3 input/output 35-39 p20-p24 port 2, pins 0, 1,2,3,4 input/output 40 ds data strobe output table 2. 40-pin dip pin identification standard mode (continued) pin no symbol function direction
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 7 figure 4. 44-pin plcc pin configuration standard mode table 3. 44-pin plcc pin identification pin no symbol function direction 1-2 gnd ground 3-4 p12-p13 port 1, pins 2,3 input/output 5 p03 port 0, pin 3 input/output 6-10 p20-p24 port 2, pins 0,1,2,3,4 input/output 11 ds data strobe output 12 nc no connection 13 r/w read/write output 14-16 p25-p27 port 2, pins 5,6,7 input/output 17-19 p04-p06 port 0, pins 4,5,6 input/output 20-21 p14-p15 port 1, pins 4,5 input/output 22 p07 port 0, pin 7 input/output 23-24 v cc power supply 25-26 p16-p17 port 1, pins 6,7 input/output p00 p33 p24 p25 p26 p27 xtal2 xtal1 p32 p23 p22 p21 p20 p02 p01 44?pin plcc v cc p04 p03 p30 p36 p37 p35 28 p34 29 p05 p06 p14 p15 p07 p16 p31 r/w as ds p12 gnd p11 p10 reset p13 nc r/rl gnd p17 v cc 17 18 7 6 1 40 39
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 8 27 xtal2 crystal oscillator output 28 xtal1 crystal oscillator input 29-31 p31-p33 port 3, pins 1,2,3 input 32 p34 port 3, pin 4 output 33 as address strobe output 34 r//rl rom/romless select input 35 reset reset input 36 p35 port 3, pin 5 output 37 p37 port 3, pin 7 output 38 p36 port 3, pin 6 output 39 p30 port 3, pin 0 input 40-41 p00-p01 port 0, pins 0,1 input/output 42-43 p10-p11 port 1, pins 0,1 input/output 44 p02 port 0, pin 2 input/output table 3. 44-pin plcc pin identification (continued) pin no symbol function direction
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 9 figure 5. 44-pin lqfp pin configuration standard mode table 4. 44-pin lqfp pin identification pin no symbol function direction 1-2 p05-p06 port 0, pins 5,6 input/output 3-4 p14-p15 port 1, pins 4,5 input/output 5 p07 port 0, pin 7 input/output 6-7 v cc power supply 8-9 p16-p17 port 1, pins 6,7 input/output 10 xtal2 crystal oscillator output 11 xtal1 crystal oscillator input 12-14 p31-p33 port 3, pins 1,2,3 input 15 p34 port 3, pin 4 output 16 as address strobe output 17 r//rl rom/romless select input p00 p33 p24 p25 p26 p27 xtal2 xtal1 p32 p23 p22 p21 p20 p02 p01 v cc p04 p03 p30 p36 p37 p35 p34 p05 p06 p14 p15 p07 p16 p31 r/w as ds p12 gnd p11 p10 reset p13 nc r/rl gnd p17 v cc 1 2 3456 7 891011 34 44 22 12 33 23 44?pin lqfp
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 10 18 reset reset input 19 p35 port 3, pin 5 output 20 p37 port 3, pin 7 output 21 p36 port 3, pin 6 output 22 p30 port 3, pin 0 input 23-24 p00-p01 port 0, pin 0,1 input/output 25-26 p10-p11 port 1, pins 0,1 input/output 27 p02 port 0, pin 2 input/output 28-29 gnd ground 30-31 p12-p13 port 1, pins 2,3 input/output 32 p03 port 0, pin 3 input/output 33-37 p20-24 port 2, pins 0,1,2,3,4 input/output 38 ds data strobe output 39 nc no connection 40 r/w read/write output 41-43 p25-p27 port 2, pins 5,6,7 input/output 44 p04 port 0, pin 4 input/output table 4. 44-pin lqfp pin identification (continued) pin no symbol function direction
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 11 figure 6. 40-pin dip pin configuration eprom mode table 5. 40-pin dip package pin identification eprom mode pin no symbol function direction 1 nc no connection 2-4 d5-d7 data 5,6,7 input/output 5-10 nc no connection 11 v cc power supply 12-14 nc no connection 15 ce chip select input 16 oe output enable input 17 epm eprom prog. mode input 18 v pp prog. voltage input 19-25 nc no connection 26 clr clear input 27 clk clock input 28-29 nc no connection clr v pp d4 d5 d6 d7 nc ce epm d3 d2 d1 d0 pgm clk v cc nc nc nc nc nc nc nc nc nc nc nc nc nc nc oe nc nc nc nc gnd nc nc nc nc 1 dip 40?pin 20 40 21
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 12 30 /pgm prog. mode input 31 gnd ground 32-34 nc no connection 35-39 d0-d4 data 0,1,2,3,4 input/output 40 nc no connection table 5. 40-pin dip package pin identification eprom mode (continued) pin no symbol function direction
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 13 figure 7. 44-pin plcc pin co nfiguration eprom programming mode table 6. 44-pin plcc pin configuration eprom programming mode pin no symbol function direction 1-2 gnd ground 3-5 nc no connection 6-10 d0-d4 data 0,1,2,3,4 input/output 11-13 nc no connection 14-16 d5-d7 data 5,6,7 input/output 17-22 nc no connection 23-24 v cc power supply 25-27 nc no connection 28 ce chip select input 29 oe output enable input 30 epm eprom prog. mode input 31 v pp prog. voltage input clr v pp d4 d5 d6 d7 nc oe epm d3 d2 d1 d0 pgm clk 44?pin plcc v cc nc nc nc nc nc nc 28 nc 29 nc nc nc nc nc nc oe nc nc nc nc gnd nc nc nc nc nc nc gnd nc v cc 17 18 7 6 1 40 39
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 14 32-39 nc no connection 40 clr clear input 41 clk clock input 42-43 nc no connection 44 /pgm prog. mode input table 6. 44-pin plcc pin configuration eprom programming mode (continued) pin no symbol function direction
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 15 figure 8. 44-pin lqfp pin configuration eprom programming mode table 7. 44-pin lqfp pin identification eprom programming mode pin no symbol function direction 1-5 nc no connection 6-7 v cc power supply 8-10 nc no connection 11 ce chip select input 12 oe output enable input 13 epm eprom prog. mode input 14 v pp prog. voltage input 15-22 nc no connection 23 clr clear input 24 clk clock input 25-26 nc no connection 27 /pgm prog. mode input 28-29 gnd ground 30-32 nc no connection clr v pp d4 d5 d6 d7 nc oe epm d3 d2 d1 d0 pgm clk 44?pin lqfp v cc nc nc nc nc nc nc 11 nc 12 nc nc nc nc nc nc oe nc nc nc nc gnd nc nc nc nc nc nc gnd nc v cc 44 1 34 33 40 22
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 16 33-37 d0-d4 data 0,1,2,3,4 input/output 38-40 nc no connection 41-43 d5-d7 data 5,6,7 input/output 44 nc no connection table 7. 44-pin lqfp pin identification eprom programming mode (continued) pin no symbol function direction
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 17 figure 9. standard mode 28-pin dip/soic pin configuration table 8. 28-pin dip/soic/plcc pin identification standard mode pin no symbol function direction 1-3 p25-p27 port 2, pins 5,6, input/output 4-7 p04-p07 port 0, pins 4,5,6,7 in/output 8v cc power supply 9 xtal2 crystal oscillator output 10 xtal1 crystal oscillator input 11-13 p31-p33 port 3, pins 1,2,3 input 14-15 p34-p35 port 3, pins 4,5 output 16 p37 port 3, pin 7 output 17 p36 port 3, pin 6 output 18 p30 port 3, pin 0 input 19-21 p00-p02 port 0, pins 0,1,2 input/output 22 v ss ground 23 p03 port 0, pin 3 input/output 24-28 p20-p24 port 2, pins 0,1,2,3,4 input/output p25 p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31 p32 p33 p34 p24 p23 p22 p21 p20 p03 v ss p02 p01 p00 p30 p36 p37 p35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin dip/soic
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 18 figure 10. standard mode 28 -pin plcc pin configuration figure 11. eprom programming mode 28-pin dip/soic pin configuration p00 p33 p24 p25 p26 p27 v dd xtal2 xtal1 p31 p32 p23 p22 p21 p20 p02 p01 v ss p04 p05 p06 p07 p03 p30 p36 p37 p35 1 11 p34 12 18 19 25 26 5 4 d5 d6 d7 nc nc nc nc v cc nc ce oe epm v pp nc d4 d3 d2 d1 d0 nc v ss pgm clk clr nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin dip/soic
ps022901-0508 pin description cmos z8 ? otp microcontrollers product specification 19 figure 12. eprom programming mode 28-pin plcc pin configuration table 9. 28-pin eprom pin identification eprom mode pin # symbol function direction 1-3 d5-d7 data 5,6,7 input/output 4-7 nc no connection 8v cc power supply 9 nc no connection 10 ce chip select input 11 oe output enable input 12 epm eprom prog. mode input 13 v pp prog. voltage input 14-18 nc no connection 19 clr clear 20 clk clock 21 /pgm prog. mode input 22 v ss ground 23 nc no connection 24-28 d0-d4 data 0,1,2,3,4 input/output clr v pp d4 d5 d6 d7 v cc nc ce oe epm d3 d2 d1 d0 pgm clk v ss nc nc nc nc nc nc nc nc nc 1 11 nc 12 18 19 25 26 5 4
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 20 electrical characteristics absolute maximum ratings stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum ra ting conditions for an extended period may affect device reliability. table 10. absolute maximum ratings parameter min max units notes ambient temperature under bias ?40 +105 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.6 +7 v 1 voltage on v dd pin with respect to v ss ?0.3 +7 v voltage on xtal1, p32, p33 and reset pins with respect to v ss ?0.6 v dd +1 v 2 total power dissipation 1.21 w maximum allowable current out of v ss 220 ma maximum allowable current into v dd 180 ma maximum allowable current into an input pin ?600 +600 a 3 maximum allowable current into an open-drain pin ?600 +600 a 4 maximum allowable output curr ent sunk by any i/o pin 25 ma maximum allowable output curren t sourced by any i/o pin 25 ma maximum allowable output current sunk by reset pin 3 ma notes 1. this applies to all pins except xtal pins and where otherwise noted. 2. there is no input protection diode from pin to v dd. 3. this excludes xtal pins. 4. device pin is not at an output low state.
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 21 total power dissipation should not exceed 1.21 w for the pa ckage. power dissipation is calculated as follows: standard test conditions the characteristics listed below apply for standa rd test conditions as noted. all voltages are referenced to gnd. positive current fl ows into the referenced pin (test load). figure 13. test load diagram capacitance t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd. total power dissipation = v dd x [i dd ? (sum of i oh ), + sum of [(v dd ? v oh ) x i oh ] + sum of (v ol x i ol ) parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf from output under test 150 pf
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 22 dc electrical characteristics table 11. dc electrical characteristics t a = 0 c to +70 c symbol parameter v cc 1 min max typical @ 25c units conditions notes v ch clock input high voltage 3.5v 0.7 v cc v cc +0.3 1.8 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 2.5 v v cl clock input low voltage 3.5v gnd -0.3 0.2 v cc 0.9 v driven by external clock generator 5.5v gnd -0.3 0.2 v cc 1.5 v v ih input high voltage 3.5v 0.7 v cc v cc +0.3 2.5 v 5.5v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 3.5v gnd -0.3 0.2 v cc 1.5 v 5.5v gnd -0.3 0.2 v cc 1.5 v v oh output high voltage low emi mode 3.5v v cc -0.4 3.3 i oh = -0.5 ma 5.5v v cc -0.4 4.8 v oh1 output high voltage 3.5v v cc -0.4 3.3 v i oh = -2.0 ma 5.5v v cc -0.4 4.8 v i oh = -2.0 ma v ol output low voltage low emi mode 3.5v 0.4 0.2 v i ol = 1.0 ma 5.5v 0.4 0.2 v i ol = 1.0 ma v ol1 output low voltage 3.5v 0.4 0.1 v i ol = +4.0 ma 2 5.5v 0.4 0.1 v i ol = +4.0 ma 2 v ol2 output low voltage 3.5v 1.2 0.5 v i ol = +10 ma 2 5.5v 1.2 0.5 v i ol = +10 ma 2 v rh reset input high voltage 3.5v .8 v cc v cc 1.7 v 3 5.5v .8 v cc v cc 2.1 v 3 v rl reset input low voltage 3.5v gnd -0.3 0.2 v cc 1.3 v 3 5.5v gnd -0.3 0.2 v cc 1.7 v 3 v olr reset output low voltage 3.5v 0.6 0.3 v i ol = 1.0 ma 3 5.5v 0.6 0.2 v i ol = 1.0 ma 3
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 23 v offset comparator input offset voltage 3.5v 25 10 mv 5.5v 25 10 mv v icr input common mode voltage range 3.5v 0 v cc -1.0v v 4 5.5v 0 v cc -1.0v v 4 i il input leakage 3.5v -1 2 0.032 a v in = 0v, v cc 5.5v -1 2 0.032 a v in = 0v, v cc i ol output leakage 3.5v -1 2 0.032 a v in = 0v, v cc 5.5v -1 2 0.032 a v in = 0v, v cc i ir reset input current 3.5v -20 -130 -65 a 5.5v -20 -180 -112 a i cc supply current 3.5v 15 5 ma @ 12 mhz 5,6 5.5v 20 15 ma @ 12 mhz 5,6 i cc1 standby current halt mode 3.5v 4 2 ma v in = 0v, v cc @ 12 mhz 5,6 5.5v 6 4 ma 5,6 3.5v 3 1.5 ma clock divide by 16 @ 12 mhz 5,6 5.5v 5 3 ma 5,6 i cc2 standby current stop mode 3.5v 10 2 a v in = 0v, v cc 7,8,9 5.5v 10 3 a v in = 0v, v cc 7,8,9 3.5v 15 7 a v in = 0v, v cc 7,8 5.5v 30 10 a v in = 0v, v cc 7,8 i all auto latch low current 3.0v 0.7 8 2.4 a 0v < v in < v cc 10 5.5v 1.4 15 4.7 a 0v < v in < v cc 10 i alh auto latch high current 3.5v -0.6 -5 -1.8 a 0v < v in < v cc 10 5.5v -1 -8 -3.8 a 0v < v in < v cc 10 table 11. dc electrical characteristics t a = 0 c to +70 c (continued) symbol parameter v cc 1 min max typical @ 25c units conditions notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 24 t por power-on reset 3.5v 2.0 ms 24 7 ms 5.5v 1.0 ms 13 4 ms v lv auto reset voltage 2.3 3.0 2.8 v 11,12 notes 1. the v cc voltage specification of 5.5 v g uarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v 2. std mode (not low emi mode) 3. z86e43/743/e44 only. 4. for analog comparator inputs when analog comparators are enabled 5. all outputs unloaded, i/o pins floating, inputs at rail. 6. cl1=cl2=22 pf. 7. same as note 5 except inputs at v cc 8. clock must be forced low, when xtal1 is clock driven and xtal2 9. wdt running 10. auto latch (mask option) selected. 11. device does function down to the auto reset voltage 12. max. temperature is 70 c table 12. dc electrical characteristics t a = -40 c to +105 c symbo l parameter v cc 1 min max typical @ 25c units conditions notes v ch clock input high voltage 4.5v 0.7 v cc v cc +0.3 2.5 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 2.5 v v cl clock input low voltage 4.5v gnd -0.3 0.2 v cc 1.5 v driven by external clock generator 5.5v gnd -0.3 0.2 v cc 1.5 v v ih input high voltage 4.5v 0.7 v cc v cc +0.3 2.5 v 5.5v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 4.5v gnd -0.3 0.2 v cc 1.5 v 5.5v gnd -0.3 0.2 v cc 1.5 v v oh output high voltage low emi mode 4.5v v cc -0.4 4.8 i oh = -0.5 ma 2 5.5v v cc -0.4 4.8 i oh = -0.5 ma 2 table 11. dc electrical characteristics t a = 0 c to +70 c (continued) symbol parameter v cc 1 min max typical @ 25c units conditions notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 25 v oh1 output high voltage 4.5v v cc -0.4 4.8 v i oh = -2.0 ma 2 5.5v v cc -0.4 4.8 v i oh = -2.0 ma 2 v ol output low voltage low emi mode 4.5v 0.4 0.2 v i ol = 1.0 ma 5.5v 0.4 0.2 v i ol = 1.0 ma v ol1 output low voltage 4.5v 0.4 0.1 v i ol = +4.0 ma 2 5.5v 0.4 0.1 v i ol = +4.0 ma 2 v ol2 output low voltage 4.5v 1.2 0.5 v i ol = +12 ma 2 5.5v 1.2 0.5 v i ol = +12 ma 2 v rh reset input high voltage 4.5v .8 v cc v cc 1.7 v 3 5.5v .8 v cc v cc 2.1 v 3 v olr reset output low voltage 4.5v 0.6 0.3 v i ol = 1.0 ma 3 5.5v 0.6 0.2 v i ol = 1.0 ma 3 v offset comparator input offset voltage 4.5v 25 10 mv 5.5v 25 10 mv v icr input common mode voltage range 4.5v 0 v cc -1.5v v 4 5.5v 0 v cc -1.5v v 4 i il input leakage 4.5v -1 2 <1 a v in = 0v, v cc 5.5v -1 2 <1 a v in = 0v, v cc i ol output leakage 4.5v -1 2 <1 a v in = 0v, v cc 5.5v -1 2 <1 a v in = 0v, v cc i ir reset input current 4.5v -18 -180 -112 a 3 5.5v -18 -180 -112 a 3 i cc supply current 4.5v 20 15 ma @ 12 mhz 5,6 5.5v 20 15 ma @ 12 mhz 5,6 i cc1 standby current halt mode 4.5v 6 2 ma v in = 0v, v cc @ 12 mhz 5,6 5.5v 6 4 ma v in = 0v, v cc @ 12 mhz 5,6 table 12. dc electrical characteristics t a = -40 c to +105 c (continued) symbo l parameter v cc 1 min max typical @ 25c units conditions notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 26 i cc2 standby current stop mode 4.5v 10 2 a v in = 0v, v cc 7,8,9 5.5v 10 3 a v in = 0v, v cc 7,8,9 4.5v 40 10 a v in = 0v, v cc 7,8 5.5v 40 10 a v in = 0v, v cc 7,8 i all auto latch low current 4.5v 1.4 20 4.7 a 0v < v in < v cc 10 5.5v 1.4 20 4.7 a 0v < v in < v cc 10 i alh auto latch high current 4.5v -1.0 -10 -3.8 a 0v < v in < v cc 10 5.5v -1.0 -10 -3.8 a 0v < v in < v cc 10 t por power-on reset 4.5v 1.0 14 4 ms 5.5v 1.0 14 4 ms v lv auto reset voltage 2.0 3.3 2.8 v 11 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. std mode (not low emi mode). 3. z86e43/743/e44 only. 4. for analog comparator inputs when analog comparators are enabled. 5. all outputs unloaded, i/o pins floating, inputs at rail. 6. cl1=cl2=22 pf. 7. same as note 5 except inputs at v cc. 8. clock must be forced low, when xtal1 is clock driven and xtal2. 9. wdt is not running. 10. auto latch (mask option) selected. 11. device does function down to the auto reset voltage. table 12. dc electrical characteristics t a = -40 c to +105 c (continued) symbo l parameter v cc 1 min max typical @ 25c units conditions notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 27 figure 14. external i/o or memory re ad/write timing (z86e43/743/e44 only) table 13. dc electrical characteristics t a = 0 c to +70 c, 12 mhz no. symbol parameter v cc 1 min max units notes 1 tda(as) address valid to as rise delay 3.5v 35 ns 2 5.5v 35 ns 2 2 tdas(a) as rise to address float delay 3.5v 45 ns 2 5.5v 45 ns 2 3 tdas(dr) as rise to read data req?d valid 3.5v 250 ns 2,3 5.5v 250 ns 2,3 12 18 1 2 16 3 8 2 20 19 13 11 9 10 15 6 7 14 17 5 4 a7?a0 a7?a0 d7?d0 in d7?d0 out ds (write) port1 ds (read) as port1 port0, dm r/w
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 28 4twas as low width 3.5v 55 ns 2 5.5v 55 ns 2 5 tdas(ds) address float to ds fall 3.5v 0 ns 5.5v 0 ns 6 twdsr ds (read) low width 3.5v 200 ns 2,3 5.5v 200 ns 2,3 7 twdsw ds (write) low width 3.5v 110 ns 2,3 5.5v 110 ns 2,3 8tddsr(dr)ds fail to read data req?d valid 3.5v 150 ns 2,3 5.5v 150 ns 2,3 9 thdr(ds) read data to ds rise hold time 3.5v 0 ns 2 5.5v 0 ns 2 10 tdds(a) ds rise to address active delay 3.5v 45 ns 2 5.5v 55 ns 2 11 tdds(as) ds rise to as fall delay 3.5v 30 ns 2 5.5v 45 ns 2 12 tdr/w(as) r/w valid to as rise delay 3.5v 45 ns 2 5.5v 45 ns 2 13 tdds(r/w) ds rise to r/w not valid 3.5v 45 ns 2 5.5v 45 ns 2 14 tddw(dsw) write data valid to ds fall (write) delay 3.5v 55 ns 2 5.5v 55 ns 2 15 tdds(dw) ds rise to write data not valid delay 3.5v 45 ns 2 5.5v 55 ns 2 16 tda(dr) address valid to read data req?d valid 3.5v 310 ns 2,3 5.5v 310 ns 2,3 17 tdas(ds) as rise to ds fall delay 3.5v 65 ns 2 5.5v 65 ns 2 table 13. dc electrical characteristics t a = 0 c to +70 c, 12 mhz (continued) no. symbol parameter v cc 1 min max units notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 29 18 tddm(as) dm valid to as rise delay 3.5v 35 ns 2 5.5v 35 ns 2 19 thds(as) ds valid to address valid hold time 3.5v 35 ns 2 5.5v 35 ns 2 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. timing numbers given are for minimum tpc. 3. when using extended memory timing, add 2 tpc standard test load all timing references use 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. for standard mode (not low-emi mode for outputs) with smr, d1 = 0, d0 = 0. table 14. dc electrical characteristics t a = -40 c to +105 c, 12 mhz no. symbol parameter v cc 1 min max units notes 1 tda(as) address valid to as rise delay 4.5v 35 ns 2 5.5v 35 ns 2 2 tdas(a) as rise to address float delay 4.5v 45 ns 2 5.5v 45 ns 2 3 tdas(dr) as rise to read data req?d valid 4.5v 250 ns 2,3 5.5v 250 ns 2,3 4twas as low width 4.5v 55 ns 2 5.5v 55 ns 2 5 tdas(ds) address float to ds fall 4.5v 0 ns 5.5v 0 ns 6 twdsr ds (read) low width 4.5v 200 ns 2,3 5.5v 200 ns 2,3 7 twdsw ds (write) low width 4.5v 110 ns 2,3 5.5v 110 ns 2,3 8tddsr(dr)ds fail to read data req?d valid 4.5v 150 ns 2,3 5.5v 150 ns 2,3 9 thdr(ds) read data to ds rise hold time 4.5v 0 ns 2 5.5v 0 ns 2 table 13. dc electrical characteristics t a = 0 c to +70 c, 12 mhz (continued) no. symbol parameter v cc 1 min max units notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 30 10 tdds(a) ds rise to address active delay 4.5v 45 ns 2 5.5v 55 ns 2 11 tdds(as) ds rise to as fall delay 4.5v 45 ns 2 5.5v 45 ns 2 12 tdr/w(as) r/w valid to as rise delay 4.5v 45 ns 2 5.5v 45 ns 2 13 tdds(r/w) ds rise to r/w not valid 4.5v 45 ns 2 5.5v 45 ns 2 14 tddw(dsw) write data valid to ds fall (write) delay 4.5v 55 ns 2 5.5v 55 ns 2 15 tdds(dw) ds rise to write data not valid delay 4.5v 55 ns 2 5.5v 55 ns 2 16 tda(dr) address valid to read data req?d valid 4.5v 310 ns 2,3 5.5v 310 ns 2,3 17 tdas(ds) as rise to ds fall delay 4.5v 65 ns 2 5.5v 65 ns 2 18 tddm(as) dm valid to as rise delay 4.5v 35 ns 2 5.5v 35 ns 2 19 thds(as) ds valid to address valid hold time 4.5v 35 ns 2 5.5v 35 ns 2 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. timing numbers given are for minimum tpc. 3. when using extended memory timing, add 2 tpc. standard test load all timing references use 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. for standard mode (not low-emi mode for outputs) with smr, d1 = 0, d0 = 0. table 14. dc electrical characteristics t a = -40 c to +105 c, 12 mhz (continued) no. symbol parameter v cc 1 min max units notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 31 figure 15. additional timing diagram table 15. additional timing table (divide-by-one mode) t a = 0 c to +70 c no symbol parameter v cc 1 min max min max units notes 1 tpc input clock period 3.5v 250 dc 166 dc ns 2,3,4 5.5v 250 dc 166 dc ns 2,3,4 2 trc,tfc clock input rise & fall times 3.5v 25 25 ns 2,3,4 5.5v 25 25 ns 2,3,4 3 twc input clock width 3.5v 100 100 ns 2,3,4 5.5v 100 100 ns 2,3,4 4 twtinl timer input low width 3.5v 100 100 ns 2,3,4 5.5v 70 70 ns 2,3,4 1 3 2 3 7 2 2 4 5 6 8 9 11 10 stop mode recovery source clock setup irqn tin clock
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 32 5 twtinh timer input high width 3.5v 5tpc 5tpc 2,3,4 5.5v 5tpc 5tpc 2,3,4 6 tptin timer input period 3.5v 8tpc 8tpc 2,3,4 5.5v 8tpc 8tpc 2,3,4 7trtin, tftin timer input rise & fall timer 3.5v 100 100 ns 2,3,4 5.5v 100 100 ns 2,3,4 8a twil int. request low time 3.5v 100 100 ns 2,3,4,5 5.5v 70 70 ns 2,3,4,5 8b twil int. request low ti me 3.5v 5tpc 5tpc 2,3,4,6 5.5v 5tpc 5tpc 2,3,4,6 9 twih int. request input high time 3.5v 5tpc 5tpc 2,3,4,5 5.5v 5tpc 5tpc 2,3,4,5 10 twsm stop mode recovery width spec 3.5v 12 12 ns 4,7 5.5v 12 12 ns 4,7 11 tost oscillator startup time 3.5v 5tpc 5tpc 4,7,8 5.5v 5tpc 5tpc 4,7,8 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc ; for a logic 0. 3. smr d1 = 0. 4. maximum frequency for in ternal system clock is 4 mhz when using low emi osc pcon bit d7 = 0. 5. interrupt request via port 3 (p31-p33). 6. interrupt request via port 3 (p30). 7. smr-d5 = 1, por stop mode delay is on. 8. for rc and lc oscillator, and for oscillator driven by clock driver. table 16. additional timing table (divide-by-one mode) t a = -40 c to +105 c no symbol parameter v cc 1 min max min max units notes 1 tpc input clock period 4.5v 250 dc 166 dc ns 2,3,4 5.5v 250 dc 166 dc ns 2,3,4 table 15. additional timing table (divide-by-one mode) t a = 0 c to +70 c (continued) no symbol parameter v cc 1 min max min max units notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 33 2 trc,tfc clock input rise & fall times 4.5v 25 25 ns 2,3,4 5.5v 25 25 ns 2,3,4 3 twc input clock width 4.5v 100 100 ns 2,3,4 5.5v 100 100 ns 2,3,4 4 twtinl timer input low width 4.5v 100 100 ns 2,3,4 5.5v 70 70 ns 2,3,4 5 twtinh timer input high width 4.5v 5tpc 5tpc 2,3,4 5.5v 5tpc 5tpc 2,3,4 6 tptin timer input period 4.5v 8tpc 8tpc 2,3,4 5.5v 8tpc 8tpc 2,3,4 7trtin, tftin timer input rise & fall timer 4.5v 100 100 ns 2,3,4 5.5v 100 100 ns 2,3,4 8a twil int. request low time 4.5v 100 100 ns 2,3,4,5 5.5v 70 70 ns 2,3,4,5 8b twil int. request low ti me 4.5v 5tpc 5tpc 2,3,4,6 5.5v 5tpc 5tpc 2,3,4,6 9 twih int. request input high time 4.5v 5tpc 5tpc 2,3,4,5 5.5v 5tpc 5tpc 2,3,4,5 10 twsm stop mode recovery width spec 4.5v 12 12 ns 4,7 5.5v 12 12 ns 4,7 11 tost oscillator startup time 4.5v 5tpc 5tpc 4,7,8 5.5v 5tpc 5tpc 4,7,8 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc ; for a logic 0. 3. smr d1 = 0. 4. maximum frequency for in ternal system clock is 4 mhz when using low emi osc pcon bit d7=0. 5. interrupt request via port 3 (p31-p33). 6. interrupt request via port 3 (p30). 7. smr-d5 = 1, por stop mode delay is on. 8. for rc and lc oscillator, and for oscillator driven by clock driver. table 16. additional timing table (divide-by-one mode) t a = -40 c to +105 c (continued) no symbol parameter v cc 1 min max min max units notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 34 handshake timing diagrams figure 16. input handshake timing figure 17. output handshake timing table 17. additional timing table (divide by two mode) t a = 0 c to +70 c no symbol parameter v cc 1 min max min max units conditions notes 1 tpc input clock period 3.5v 62.5 dc 250 dc ns 2,6,4 5.5v 62.5 dc 250 dc ns 2,6,4 2 trc,tfc clock input rise & fall times 3.5v 15 25 ns 2,6,4 5.5v 15 25 ns 2,6,4 3 twc input clock width 3.5v 31 31 ns 2,6,4 5.5v 31 31 ns 2,6,4 1 3 2 4 5 6 data in valid next data in valid delayed dav delayed rdy data in data in dav (input) rdy (output) data out valid next data out valid delayed dav delayed rdy data out dav (output) rdy (input) 7 8 9 10 11
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 35 4 twtinl timer input low width 3.5v 70 70 ns 2,6,4 5.5v 70 70 ns 2,6,4 5 twtinh timer input high width 3.5v 5tpc 5tpc 2,6,4 5.5v 5tpc 5tpc 2,6,4 6 tptin timer input period 3.5v 8tpc 8tpc 2,6,4 5.5v 8tpc 8tpc 2,6,4 7trtin, tftin timer input rise & fall timer 3.5v 100 100 ns 2,6,4 5.5v 100 100 ns 2,6,4 8a twil int. request low time 3.5v 70 70 ns 2,6,4,5 5.5v 70 70 ns 2,6,4,5 8b twil int. request low time 3.5v 5tpc 5tpc 2,6,4,5 5.5v 5tpc 5tpc 2,6,4,5 9 twih int. request input high time 3.5v 5tpc 5tpc 2,6,4,5 5.5v 5tpc 5tpc 2,6,4,5 10 twsm stop mode recovery width spec 3.5v 12 12 ns 6,7 5.5v 12 12 ns 6,7 11 tost oscillator startup time 3.5v 5tpc 5tpc 6,7 5.5v 5tpc 5tpc 6,7 12 twdt watchdog timer delay time before timeout 3.5v 7 10 ms d0 =0 8,9 5.5v 3.5 5 ms d1 = 0 5,11 3.5v 14 20 ms d0 =1 5,11 5.5v 7 10 ms d1 = 0 5,11 3.5v 28 40 ms d1 = 0 5,11 5.5v 14 20 ms d1 = 1 5,11 3.5v 112 160 ms d0 = 1 5,11 5.5v 56 80 ms d1 = 1 5,11 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. timing reference uses 0.7 vc0 for a logic 1 and 0.2 vgc for a logic 0. 3. smr d1 = 0. 4. smr-d5 = 1, por stop mode delay is on 5. interrupt request via port 3 (p31-p33) 6. interrupt request via port 3 (p30). 7. maximum frequency for internal system clock is 2 mhz when using low emi osc pcon bit d7 = 0 8. reg. wdtmr. 9. using internal rc. table 17. additional timing table (divide by two mode) t a = 0 c to +70 c (continued) no symbol parameter v cc 1 min max min max units conditions notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 36 table 18. additional timing table (divide by two mode) t a = -40 c to +105 c no symbol parameter v cc 1 min max min max units conditions notes 1 tpc input clock period 3.5v 62.5 dc 250 dc ns 2,6,4 5.5v 62.5 dc 250 dc ns 2,6,4 2 trc,tfc clock input rise & fall times 3.5v 15 25 ns 2,6,4 5.5v 15 25 ns 2,6,4 3 twc input clock width 3.5v 31 31 ns 2,6,4 5.5v 31 31 ns 2,6,4 4 twtinl timer input low width 3.5v 70 70 ns 2,6,4 5.5v 70 70 ns 2,6,4 5 twtinh timer input high width 3.5v 5tpc 5tpc 2,6,4 5.5v 5tpc 5tpc 2,6,4 6 tptin timer input period 3.5v 8tpc 8tpc 2,6,4 5.5v 8tpc 8tpc 2,6,4 7trtin, tftin timer input rise & fall timer 3.5v 100 100 ns 2,6,4 5.5v 100 100 ns 2,6,4 8a twil int. request low time 3.5v 70 70 ns 2,6,4,5 5.5v 70 70 ns 2,6,4,5 8b twil int. request low time 3.5v 5tpc 5tpc 2,6,4,5 5.5v 5tpc 5tpc 2,6,4,5 9 twih int. request input high time 3.5v 5tpc 5tpc 2,6,4,5 5.5v 5tpc 5tpc 2,6,4,5 10 twsm stop mode recovery width spec 3.5v 12 12 ns 6,7 5.5v 12 12 ns 6,7 11 tost oscillator startup time 3.5v 5tpc 5tpc 6,7 5.5v 5tpc 5tpc 6,7
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 37 pin functions eprom programming mode d7-d0 data bus. the data can be read from or written to ex ternal memory through the data bus. v cc power supply. this pin must supply 5 v during the eprom read mode and 6 v dur- ing other modes. ce chip enable (active low). this pin is active during eprom read mode, program mode, and program verify mode. oe output enable (active low). this pin drives the direction of the data bus. when this pin is low, the data bus is output , when high, the data bus is input. epm eprom program mode. this pin controls the different eprom program mode by applying different voltages. v pp program voltage. this pin supplies the program voltage. pgm program mode (active low). when this pin is low, the data is programmed to the eprom through the data bus. 12 twdt watchdog timer delay time before timeout 3.5v 7 10 ms d0 =0 8,9 5.5v 3.5 5 ms d1 = 0 5,11 3.5v 14 20 ms d0 =1 5,11 5.5v 7 10 ms d1 = 0 5,11 3.5v 28 40 ms d1 = 0 5,11 5.5v 14 20 ms d1 = 1 5,11 3.5v 112 160 ms d0 = 1 5,11 5.5v 56 80 ms d1 = 1 5,11 notes 1. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v and the v cc voltage specification of 3.5 v guarantees only 3.5 v. 2. timing reference uses 0.7 vc0 for a logic 1 and 0.2 vgc for a logic 0. 3. smr d1 = 0. 4. smr-d5 = 1, por stop mode delay is on 5. interrupt request via port 3 (p31-p33) 6. interrupt request via port 3 (p30). 7. maximum frequency for internal system clock is 2 mhz when using low emi osc pcon bit d7 = 0 8. reg. wdtmr. 9. using internal rc. table 18. additional timing table (divide by two mode) t a = -40 c to +105 c (continued) no symbol parameter v cc 1 min max min max units conditions notes
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 38 clr clear (active high). this pin resets the internal address counter at the high level. clk address clock. this pin is a clock input. the internal address counter increases by one for each clock cycle. application precaution the production test-mode environment may be enabled accidentally during normal opera- tion if excessive noise surges above v cc occur on pins p31 and reset . in addition, processor operatio n of z8 otp devices may be affected by excessive noise surges on the v pp , epm, oe pins while the microcontro ller is in standard mode. recommendations for dampening voltage surges in both test and otp mode include the following: ? using a clamping diode to v cc ? adding a capacitor to the affected pin ? enable eprom/test mode disable otp option bit. standard mode xtal crystal 1 (time-based input) . this pin connects a paralle l-resonant crystal, ceramic resonator, lc, rc network, or external single -phase clock to the on -chip oscillator input. xtal2 crystal 2 (time-based output). this pi n connects a parallel-resonant crystal, ceramic resonator, lc, or rc network to the on-chip oscillator output. r/w read/write (output, write low). the r/w signal is low when the ccp is writing to the external program or data memory (z86e43/743/e44 only). reset reset (input, active low). reset will in itialize the mcu. reset is accomplished either through power-on, watchdog timer reset, stop mode recovery, or external reset. during power-on reset and watchdog timer rese t, the internally ge nerated reset drives the reset pin low for the por time. any devic es driving the reset line must be open-drain in order to avoid damage from a possible conflict during reset conditions. pull-up is pro- vided internally. after the por time, reset is a schmitt-triggered input. (reset is available on z86e43/743/e44 only.) to avoid asynchronous and noisy reset problems , the z86e43/743/e44 is equipped with a reset filter of four external clocks (4tpc). if th e external reset signal is less than 4tpc in duration, no reset occurs. on the fifth clock af ter the reset is detected, an internal rst sig- nal is latched and held for an internal register count of 18 external clocks, or for the dura- tion of the external reset, whichever is longer. during the reset cycle, ds is held active low while as cycles at a rate of tpc/2. program execution begins at location 000ch, 5- 10 tpc cycles after reset is released. for power-on reset, the reset output time is 5 ms.
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 39 the z86e43/743/e44 does not reset wdtmr, smr, p2m, and p3m registers on a stop- mode recovery operation. romless (input, active low). this pin, when connected to gnd, disables the internal rom and forces the device to function as a z86c90/c89 romless z8. (note that, when left unconnected or pulled high to v cc , the device functions nor when using in rom mode in high emi (noisy) environment, the romless pins should be connected directly to v cc . ds (output, active low). data st robe is activated once for each external memory transfer. for a read operation, data must be av ailable prior to the trailing edge of ds . for write operations, the falling edge of ds indicates that output data is valid. as (output, active low). address strobe is pu lsed once at the beginn ing of each machine cycle for external memory transfer. address ou tput is from port 0/port 1 for all external programs. memory address transfers are valid at the trailing edge of as . under program control, as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. port 0 (p07-p00) . port 0 is an 8-bit, bidirectional, cmos-compatible i/0 port. these eight i/o lines can be configured under software co ntrol as a nibble i/0 port, or as an address port for interfacing external memory. the in put buffers are schmitt-triggered and nibble programmed. either nibble output that can be globally programmed as push-pull or open- drain. low emi output buffers can be globally programmed by the software. port 0 can be placed under handshake control. in handshak e mode, port 3 lines p3 2 and p35 are used as handshake control lines. the ha ndshake direction is determ ined by the configuration (input or output) assigned to port 0?s upper nibble. the lower nibble must have the same direction as the upper nibble. for external memory references, port 0 provid es address bits a11-a8 (lower nibble) or al 5-a8 (lower and upper nibble) depending on the required address space. if the address range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for addr essing. if one or both nibbles are needed for i/o operation, they must be configured by wr iting to the port 0 mode register. in romless mode, after a hardware reset, port 0 is confi gured as address lines al 5-a8, and extended timing is set to accommodate slow memory access. the initia lization routine can include re-configuration to eliminate th is extended timing mode. in rom mode, port 0 is defined as input after reset. port 0 can be set in the high-impedance mode if selected as an address output state, along with port 1 and the control signals as , ds , and r/w ( figure 18 ). note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 40 figure 18. port 0 configuration port 1 (p17-p10) . port 1 is an 8-bit, bidirectiona l, cmos-compatible port with multi- plexed address (a7-a0) and data (d7-d0) ports. these eight i/o lines can be pro- grammed as inputs or outputs or can be conf igured under software control as an address/ data port for interfacing external memory. the input buffers are schmitt-triggered and the output buffers can be globally programmed as either push-pull or open-drain. low emi output buffers can be globally programmed by the software. port 1 can be placed under handshake control. in this co nfiguration, port 3, lines p33 and p34 are used as the hand- shake controls rdy1 and dav1 (ready and data available). to interface external mem- ory, port 1 must be programmed for the mu ltiplexed address/data mo de. if more than 256 external locations are required, port 0 outputs the additional lines (see figure 19 ). oen out in pad auto latch 1.5 2.3 hysteresis v cc @ v cc = 5.0v r ~ ~ 500 k open-drain port 0 (i/o) mcu handshake controls dav0 and rdy0 (p32 and p35) 4 4
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 41 port 1 can be placed in the high-imp edance state along with port 0, as , ds , and r/w , allowing the z86e43/743/e 44 to share common resource s in multiprocessor and dma applications. in rom mode, port 1 is defined as input after reset. figure 19. port 1 configuration (z86e43/743/e44 only) port 2 (p27-p20) . port 2 is an 8-bit, bidirectiona l, cmos-compatible i/o port. these eight i/o lines can be configured under softwa re control as an input or output, indepen- dently. all input buffers are schmitt-triggere d. bits programmed as outputs can be glo- bally programmed as either push-pull or open-drain. low emi output buffers can be globally programmed by the software. when us ed as an i/o port, port 2 can be placed under handshake control. after reset, port 2 is defined as an input. port 2 (i/o) open out in pad auto latch 1.5 2.3 hysteresis r ~ ~ 500 k open drain mcu handshake controls dav1 and rdy1 (p33 and p34)
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 42 in handshake mode, port 3 lines p31 and p3 6 are used as handshak e control lines. the handshake direction is determined by the configuration (input or output) assigned to bit 7 of port 2 (see figure 20 ). figure 20. port 2 configuration port 3 (p37-p30) . port 3 is an 8-bit, cmos-compatible port with four fixed inputs (p33- p30) and four fixed outputs (p37-p34). these eight lines can be configured by software for interrupt and handshake cont rol functions. port 3, pin 0 is schmitt- triggered. p31, p32, and p33 are standard cmos inputs with si ngle trip point (no au to latches) and p34, p35, p36, and p37 are push-pull output lines. low emi output buffers can be globally pro- grammed by the software. two on-board comp arators can process analog signals on p31 port 2 (i/o) open out in pad auto latch 1.5 2.3 hysteresis r ~ ~ 500 k open drain mcu handshake controls dav2 and rdy2 (p31 and p36)
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 43 and p32 with reference to th e voltage on p33. the analog function is enabled by setting the d1 of port 3 mode register (p3m). the comparator output can be outputted from p34 and p37, respectively, by setting pcon register bit d0 to 1 state. for the interrupt func- tion, p30 and p33 are falling edge triggered interrupt inputs. p31 and p32 can be pro- grammed as falling, rising or both ed ges triggered inte rrupt inputs (see figure 21 ). access to counter/timer 1 is made through p31 (t in ) and p36 (t out ). handshake tines for port 0, port 1, and port 2 are also available on port 3 (see table 19 ). when enabling or disabling analog mode, the following is recommended: 1. allow two nop decays before re ading this comparator output. 2. disable global interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. 3. irq register bits 3 to 0 must be cleared after enabling analog mode. p33-p30 differs from the z86c33/c43/233/243 in that there is no clamping diode to v cc due to the eprom hi gh-voltage circuits. exceeding the v ih maximum specification duri ng standard operating mode may cause the devi ce to enter eprom mode. note: note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 44 figure 21. port 3 configuration mcu port 3 + - + - irq2, t in , p31 data latch 0 = digital 1 = analog d1 r247 = p3m dig. anl. (i/o or control) auto latch r ~ ~ 500 k p30 data latch irq3 irq0, p32 data latch irq1, p33 data latch from stop-mode recovery source p30 p31 (an1) p32 (an2) p33 (ref)
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 45 comparator inputs . port 3, p31, and p32, each have a comparator front end. the com- parator reference voltage p33 is common to both comparator s. in analog mode, p31 and p32 are the positive input of the comparators a nd p33 is the reference voltage of the com- parators. auto latch . the auto latch puts valid cmos le vels on all cmos inputs (except p33- p31) that are not externally driven. whether th is level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node , reduces excessive supply current flow in the input buffer. auto latches are available on port 0, port 1, port 2, and p30. there are no auto latches on p31, p32, and p33. low emi emission . the z86e43/743/e44 can be programmed to operate in a low emi emission mode in the pcon register. the osc illator and all i/o ports can be programmed as low emi emission mode independently . use of this fe ature results in: ? the pre-drivers slew rate reduced to 10 ns typical. ? low emi output drivers have resi stance of 200 ohms (typical). ? low emi oscillator. ? internal sclk/tclk= xtal operation limited to a maximum of 4 mhz - 250 ns cycle time, when low emi oscillator is selected. for emulation only: do not set the emulator to emulat e port 1 in low emi mode. port 1 must always be configured in standard mode. table 19. port 3 pin assignments pin i/o ctc1 analog interrupt p0 hs p1 hs p2 hs ext p30 in irq3 p31 in t in an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 d/r p34 out an1-out r/d dm p35 out r/d p36 out t out r/d p37 out an2-out note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 46 functional description the mcu incorporates the following special fu nctions to enhance the standard z8 archi- tecture to provide the user w ith increased design flexibility. reset . the device is reset in one of three ways: 1. power-on reset 2. watchdog timer 3. stop mode recovery source having the auto power-on reset circuitry built-in, the mcu does not need to be connected to an external power-on re set circuit. the reset time is t por . the mcu does not re-initialize wdtmr, smr, p2m, and p3m registers to their reset values on a stop mode recovery operation. the device v cc must rise up to the operating v cc specification before the t por expires. program memory . the mcu can address up to 4/8/16 kb of internal program memory (see figure 22 ). the first 12 bytes of program memo ry are reserved for the interrupt vec- tors. these locations contain six 16-bit vectors that correspond to the six available inter- rupts. for eprom mode, byte 12 ( 000ch ) to address 4095 ( 0fffh )/8191 ( 1fffh )/ 16384 ( 3fffh ), consists of programmable eprom . after reset, the program counter points at the address 000ch , which is the starting addr ess of the user program. in romless mode, the z86e43/743/e44 can ad dress up to 64 kb of external program memory. the rom/romless option is only available on the 44-pin devices. note: note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 47 figure 22. program memory map eprom protect . when in rom protect mode, and ex ecuting out of external program memory, instructions ldc, ldci, lde, and ldei cannot read internal program mem- ory. when in eprom protect mode and executing out of internal program memory, instruc- tions ldc, ldci, lde, and ldei can read internal program memory. data memory (dm ) . in rom mode, the z86e43/743/e44 can address up to 60156/48 kb of external data memory beginning at location 4096/8192/16384. in romless mode, the z86e43/743/e44 can address up to 64 kb of data memory. external data memory may be included with, or separated from, the external program memory space. dm , an optional i/0 function that can be programmed to appear on pin p34, is used to distinguish between data and program memory space ( figure 23 ). the state of the dm signal is controlled by the type of instruction being executed. an ldc opcode refe rences program (dm inac- tive) memory, and an lde inst ruction references data (dm active low) memory. 12 11 10 9 8 7 6 5 4 3 2 1 0 irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 interrupt vector (lower byte) interrupt vector (upper byte) location of first byte of instruction executed after reset on-chip eprom external rom and ram 65535 4096/8192/16384 4095/8191/16383 rom module irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 external rom and ram romless module (z86e43/743/e44 only)
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 48 figure 23. da ta memory map register file . the register file consists of three i/o port registers, 236/125 general-pur- pose registers, 15 control and status registers, and three system configuration registers in the expanded register group. the instructions can access registers directly or indirectly through an 8-bit address field. this allows a sh ort 4-bit register address using the register pointer (see figure 24 ). in the 4-bit mode, the register f ile is divided into 16 working reg- ister groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working-register group. register group e0-ef can only be accessed through working register and indirect addressing modes. external data memory 65535 4096 /8192/16384 4095 /8191/16383 0 not addressable eprom external data memory romless mode (z86e43/743/e44 only) note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 49 figure 24. register pointer register expanded register file (erf). the register file has been expanded to allow for addi- tional system control registers, mapping of ad ditional peripheral de vices and input/output ports into the register address area. the z8 register address space ro through r15 is implemented as 16 groups of 16 registers per group (see figure 26 ). these register banks are known as the expanded register file (erf). the low nibble (d3-d0) of the register poin ter (rp) select the active erf bank, and the high nibble (d7-d4) of register rp select the working register group. three system con- figuration registers reside in the expanded register file at bank fh: pcon, smr, and wdtmr. the rest of the expanded register is not physically implemented and is reserved for future expansion. r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register group working register group default after reset = 00h
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 50 figure 25. register pointer this upper nibble of the register file addresses ef 80 provided by the register pointer specifies r232 (register pointer) r7 r6 r5 r4 r3 r2 r1 r0 the active working-register group. the lower nibble of the register file addresses provided by the instruction points to the specified register. specified working register group register group 1 register group 0 i/o ports r15 to r0 r15 to r4 r3 to r0 7f 70 6f 60 5f 50 4f 40 3f 30 2f 20 1f 10 0f 00 ff f0 * expanded register group (0) is selected in this figure by handling bits d3 to d0 as ?0? in register r253 (rp).
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 51 figure 26. expanded register file architecture general-purpose registers (gpr) . these registers are undefined after the device is powered up. the registers keep their last valu e after any reset, as long as the reset occurs in the v cc voltage-specified operating range. the register r254 is general-purpose on z86e33/733/e34. r254 and r255 are set to 00h after any reset or stop mode recovery. 76543 21 0 register pointer expanded register group pointer working register group pointer z8 reg. file %ff %f0 %7f %0f %00 reserved notes: u = unknown * will not be reset with a stop-mode recovery. ** will not be reset with a stop-mode recovery, except bit d0. register 0000 0 00 0 0000 0 00 0 0000 0 00 0 0000 0 00 0 uuuu u uu u 0000 0 00 0 uuuu u uu u uuuu u uu u uuuu u uu u 1111 1 11 1 1001 1 00 0 0000 0 00 0 uuuu u uu u uuuu u uu u uuuu u uu 0 reset condition uu01 1 0 1 u uuuu u 0 0 u 0100 0 00 0 1111 1 10 1 reset condition 111 uuuu 1 uuu uu uu u uuu uu uu u uuu uu uu u expanded reg. group (0) register % (0) 03 % (0) 02 % (0) 01 % (0) 00 p3 p2 p1 p0 * * % ff % fe % fd % fc % fb % fa % f9 % f8 % f7 % f6 % f5 % f4 % f3 % f2 % f1 % f0 spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr reserved ? * * * * ** % (f) 0f % (f) 0e % (f) 0d % (f) 0c % (f) 0b % (f) 0a % (f) 09 % (f) 08 % (f) 07 % (f) 06 % (f) 05 % (f) 04 % (f) 03 % (f) 02 % (f) 01 % (f) 00 wdtmr reserved smr2 reserved smr reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pcon ? for romless condition: ?10110110? expanded reg. group (f) register d7 d6 d5 d4 d3 d2 d1 d0 reset condition
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 52 ram protect. the upper portion of the ram?s address spaces 80h to efh (excluding the control registers) can be protected from read ing and writing. this op tion can be selected during the eprom programming mode. after this option is selected, the user can activate this feature from the internal eprom. d6 of the imr control register (r251) is used to turn off/on the ram protect by loading a 0 or 1, respectively. a ?1? in d6 indicates ram protect enabled. stack . the z86e43/743/e44 external data memory or the internal register file can be used for the stack. the 16-bit stack pointer (r254-r2 55) is used for the external stack, which can reside anywhere in the data memory for romless mode, but only from 4096/8192/ 16384 to 65535 in rom mode. an 8-bit stack po inter (r255) is used for the internal stack on the z8 that resides within the 236 general-purpose registers (r4-r239). sph (r254) can be used as a general-purpose register when using internal stack only. r254 and r255 are set to 00h after any reset or stop mode recovery. counter/timers . there are two 8-bit programmable counter/timers (t0 and t1), each driven by its own 6-bit programmable prescaler. the ti prescaler is driven by internal or external clock sources; however, the to prescaler is driven by the internal clock only (see figure 27 ). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decremen ts the value (1 to 256), that has been loaded in to the counter. when the coun ter reaches the end of count, a timer interrupt request, irq4 (t 0) or irq5 (t1), is generated. the counters can be programmed to start, stop , restart to continue, or restart from the ini- tial value. the counters can also be program med to stop upon reach ing one (single pass mode) or to automatically relo ad the initial value and contin ue counting (modulo-n contin- uous mode). the counters, but not the prescalers, can be r ead at any time without disturbing their value or count mode. the clock source for t1 is u ser-definable and can be either the internal microprocessor clock divided by four, or an external signal input through port 3. the timer mode register configures the external tim er input (p31) as an external clock, a trig- ger input that can be retriggera ble or non-retriggerable, or as a gate input for the internal clock. port 3 line p36 serves as a timer output (t out ) through which t0, t1, or the inter- nal clock can be output. the counter/timers can be cascaded by connecting the t0 output to the input of t1.
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 53 figure 27. counter/ timer block diagram interrupts . the mcu has six different interrupts from six different sources. the inter- rupts are maskable and prioritized ( figure 28 ). the six sources are divided as follows: four sources are claimed by port 3 lines p33-p30) and two in counter/timers. the interrupt mask register globally or individually en ables or disables the six interrupt requests ( table 20 ). t1 irq5 internal clock clock logic external clock 2 internal clock gated clock triggered clock t in p31 osc current value write write read internal data bus register 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register 4 t0 irq4 current value write read internal data bus register 6-bit down counter 8-bit down counter pre0 initial value register t0 initial value register 4 16 2 t out p36 write
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 54 figure 28. interru pt block diagram table 20. interrupt types, sources, and vectors name source vector location comments irq0 dav0 , irq0 0,1 external (p32), ri sing/falling edge triggered irq1 irq1 2,3 external (p33 ), falling edge triggered irq2 dav2 , irq2, t in 4,5 external (p31), risi ng/falling edge triggered irq3 irq3 6,7 external (p30 ), falling edge triggered 1rq4 t0 8,9 internal irq5 t1 10,11 internal irq imr ipr 6 priority logic interrupt request global interrupt enable vector select interrupt edge select irq0 irq2 irq (d6, d7) irq1, 3, 4, 5
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 55 when more than one interrupt is pending, pr iorities are resolved by a programmable prior- ity encoder that is controlled by the interrupt priority register (ipr). an interrupt machine cycle is activated when an interrupt request is granted. thus, di sabling all subsequent interrupts, saves the program counter and stat us flags, and then branches to the program memory vector location reserv ed for that interrupt. all in terrupts are vectored through locations in the program memory . this memory location and th e next byte contain the 16- bit starting address of the interrupt service ro utine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine whic h of the interrupt re quests need service. an interrupt resulting from an 1 is mapped into irq2, an d an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 may be rising, falling or both edge trig- gered, and are programmable by the user. the so ftware may poll to identify the state of the pin. programming bits for the interru pt edge select are located in bits d7 and d6 of the irq register (r250). the configuration is shown in table 21 . clock . the on-chip oscillator has a high-gain, parallel-resonant amp lifier for connection to a crystal, rc, ceramic resonator, or any su itable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 10 khz to 16 mhz max, with a series resistance (rs) less than or equal to 100 . the crystal should be connected across xtal1 and xtal2 using the vendor?s recom- mended capacitor values from eac h pin directly to device pin ground. the rc oscillator option can be selected in the programming mo de. the rc oscillator configuration must be an external resistor connected from xtal1 to xtal2, with a frequency-setting capacitor from xtal1 to ground ( table 29 ). table 21. irq register configuration iro interrupt edge d7 d6 p31 p32 00ff 01fr 10rf 11r/fr/f notes 1. f = falling edge 2. r = rising edge
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 56 figure 29. oscillator configuration power-on reset (por) . a timer circuit clocked by a dedi cated on-board rc oscillator is used for the power-on reset (por) tim er function. the por timer allows v cc and the oscillator circuit to stabilize befo re instruction execution begins. the por timer circuit is a one-shot time r triggered by one of three conditions: 1. power fail to power ok status 2. stop mode recovery (if d5 of smr=0) 3. wdt time-out the por time is a nominal 5 ms. bit 5 of the stop mode register (smr) determines whether the por timer is by-passed after stop mode recovery (typic al for an external clock and rc/lc oscillators with fast start up times). halt . turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external interrupt irq0, irq1, and irq2 remain active . the device is recovered by interrupts, either externally or internally generated. an inte rrupt request must be executed (enabled) to exit halt mode. af ter the interrupt service routine, the program continues from the instruction after the halt. in order to enter stop or halt mode, it is neces- sary to first flush the instruction pipeline to avoid suspending execution in mid-instruc- tion. to do this, you must execute a nop (opcode = ffh ) immediately before the appropriate sleep instruction, that is: c1 xtal1 xtal2 lc c2 c1 c2 external clock rc xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 l r ceramic resonator or crystal c1, c2 = 33 pf typ * f = 8 mhz * typical value including pin parasitics v ss ** c1, c2 = 22 pf c1 @ 5v v cc (typ) c1 = 100 pf * r = 2k * f = 6 mhz * l = 130 h * f = 3 mhz
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 57 or stop . this instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 microamperes or less. stop mode is terminated by one of the following resets: either by wdt time -out, por, a stop mode recovery source, which is defined by the smr register or extern al reset. this causes the processor to restart the application program at address 000ch. port configuration register (pcon) . the pcon register configures the ports individu- ally; comparator output on port 3, open-drain on port 0 and port 1, low emi on ports 0, 1, 2 and 3, and low emi oscillator. the pcon regist er is located in the expanded register file at bank f, location 00 ( figure 30 ). figure 30. port configuration register (pcon) (write only) ff nop ; clear the pipeline 6f stop ; enter stop mode ff nop ; clear the pipeline 7f halt ; enter halt mode pcon (fh) 00h 0 p34, p37 standard output* 1 p34, p37 comparator output* d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 port 1 open-drain 1 port 1 push-pull active* 0 port 0 open-drain 1 port 0 push-pull active* 0 port 1 low emi 1 port 1 standard* 0 port 2 low emi 1 port 2 standard* 0 port 3 low emi 1 port 3 standard* 0 low emi 1 standard low emi character * default setting after reset 0 port 0 low emi 1 port 0 standard*
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 58 comparator output port 3 (d0). bit 0 controls the comparat or output in port 3. a ?1? in this location brings the comparator outputs to p34 and p37, and a ?0? releases the port to its standard i/o configuratio n. the default value is 0. port 1 open-drain (d1). port 1 can be configured as an open-drain by resetting this bit (d1=0) or configured as push-p ull active by setting this bit (d1=1). the default value is 1. port 0 open-drain (d2). port 0 can be configured as an open-drain by resetting this bit (d2=0) or configured as push-p ull active by setting this bit (d2=1). the default value is 1. low emi port 0 (d3). port 0 can be configured as a low emi port by resetting this bit (d3=0) or configured as a standard port by setting this bit (d3=1). the default value is 1. low emi port 1 (d4). port 1 can be configured as a low emi port by resetting this bit (d4=0) or configured as a standard port by se tting this bit (d4=1). the default value is 1. the emulator does not support port 1 low emi mode and must be set d4 = 1. low emi port 2 (d5). port 2 can be configured as a low emi port by resetting this bit (d5=0) or configured as a standard port by se tting this bit (d5=1). the default value is 1. low emi port 3 (d6). port 3 can be configured as a low emi port by resetting this bit (d6=0) or configured as a standard port by setting this bit (d6=1). the default value is 1. low emi osc (d7). this bit of the pcon register controls the low emi noise oscilla- tor. a ?1? in this location conf igures the oscillator with standa rd drive. while a ?0? config- ures the oscillator with low noise drive, ho wever, it does not affect the relationship of sclk and xtal. the low emi mode will reduce the drive of the oscillator (osc). the default value is 1. 4 mhz is the maximum external clo ck frequency when running in the low emi oscillator mode. stop-mode recovery register (smr). this register selects the clock divide value and determines the mode of stop mode recovery ( figure 31 ). all bits are write only except bit 7 which is a read only. bit 7 is a flag bit that is hardwa re set on the condition of stop recovery and reset by a power-on cycle. b it 6 controls whether a low or high level is required from the recovery source. bit 5 controls the reset delay after recovery. bits 2, 3, and 4 of the smr register specify the stop mo de recovery source. the smr is located in bank f of the expanded register file at address 0bh. note: note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 59 figure 31. stop mode recovery register (wri te-only except bit d7, which is read-only) sclk/tclk divide-by-16 select (d0) . this bit of the smr controls a divide-by-16 prescaler of sclk/tclk. the purpose of th is control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources coun ter/timers and interrupt logic). external clock divide-by-two (d1) . this bit can eliminate the oscillator divide-by-two circuitry. when this bit is 0, the system clock (sclk) and timer clock (tclk) are equal to the external clock frequency divided by tw o. the sclk/tclk is equal to the external clock frequency when this bit is set (d1=1). using this bit together with d7 of pcon fur- ther helps lower emi (that is, d7 (pcon) = 0, d1 (smr) = 1). the default setting is zero. stop mode recovery source (d2, d3, and d4) . these three bits of the smr register specify the wake up source of the stop mode recovery ( figure 32 ). table 22 shows the smr source selected with the setting of d2 to d4. p33-p31 cannot be used to wake up smr (fh) 0b 0 off** 1 on d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 sclk/tclk = xtal/2* 1 sclk/tclk = xtal external clock divide-by-2 000 por only and/or external reset* 001 p30 stop-mode recovery source 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 0 off 1 on stop delay 0 low* 1 high stop recovery level 0 por* 1 stop recovery stop flag (read only) * default setting after reset ** default setting after r eset and stop-mode recovery
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 60 from stop mode when programmed as analog inputs. when the stop mode recovery sources are selected in this register then sm r2 register bits d0, d1 must be set to zero. if the port 2 pin is configured as an output, this output level will be read by the smr circuitry. figure 32. stop mode recovery source note: to p o r reset to p3 3 da ta latch and irq1 digital/analog mode select (p3m) p33 from pads stop-mode recovery edge select (smr) mux smr d4 d3 d2 000 smr d4 d3 d2 100 smr d4 d3 d2 101 smr d4 d3 d2 00 1 smr d4 d3 d2 111 smr d4 d3 d2 110 01 0 01 1 v dd p30 p31 p32 p33 p27 p20 p23 p20 p27 smr d1 d0 00 v dd p20 p23 smr2 d1 d0 01 p20 p23 smr2 d1 d0 10
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 61 stop mode recovery delay select (d5) . the 5 ms reset delay after stop mode recov- ery is disabled by programming this bit to a zero. a ?1? in this bit will cause a 5 ms reset delay after stop mode recovery. the defa ult condition of this bit is 1. if the fast wake up mode is selected, the stop mode rec overy source needs to be kept active for at least 5tpc. stop mode recovery level select (d6) . a ?1? in this bit defines that a high level on any one of the recovery sources wakes the mcu from stop mode. a 0 defines low level recovery. the default value is 0. cold or warm start (d7) . this bit is set by the device upon entering stop mode. a ?0? in this bit indicates that the device has been reset by por (cold). a ?1? in this bit indicates the device was awakened by a smr source (warm). stop mode recovery register 2 (smr2) . this register contains additional stop mode recovery sources. when the stop mode recovery sources are selected in this register then smr register bits d2, d3, and d4 must be 0. watchdog timer mode register (wdtmr) . the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is disabled after power-on table 22. stop mode recovery source d4 d3 d2 smr source selection 000por recovery only 001p30 transition 010p31 transition (not in analog mode) 011p32 transition (not in analog mode) 100p33 transition (not in analog mode) 101p27 transition 110logical nor of port 2 bits 0-3 111logical nor of port 2 bits 0-7 smr:10 operation d1 do description of action 0 0 por and/or external reset recovery 0 1 logical and of p20 through p23 1 0 logical and of p20 through p27
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 62 reset and initially enabled by executing the wd t instruction and refre shed on subsequent executions of the wdt instruction. the wdt is driven either by an on-board rc oscilla- tor or an external oscillator from xtal1 pin. the por clock source is selected with bit 4 of the wdt register. execution of the wdt instruction a ffects the z (zero), s (sign), and v (overflow) flags. wdt time-out period (d0 and d1) . bits 0 and 1 control a tap circuit that determines the time-out periods that can be obtained ( table 23 ). the default value of do and dl are 1 and 0, respectively. wdt during halt mode (d2) . this bit determines whethe r or not the wdt is active during halt mode. a ?1? indicates that the wdt is active during halt. a ?0? disables the wdt in halt mode. the defa ult value is ?1 ?. wdt during stop mode (d3). this bit determines whether or not the wdt is active during stop mode. a ?1? indicates active during stop. a ?0? disables the wdt du ring stop mode. this is applicable only when the wdt clock source is the internal rc oscillator. clock source for wdt (d4) . this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscillator is bypassed and the por and wdt clock source is driven from the external pin, xtal1, and the wdt is stopped in stop mode. the defa ult configuration of this bit is 0, which selects the rc oscillator. permanent wdt . when this feature is enabled, the wdt is enabled after reset and will operate in run and halt mode. the control b its in the wdtmr do not affect the wdt operation. if the clock source of the wdt is the internal rc oscillator, then the wdt will run in stop mode. if the clock source of the wdt is the xtal1 pin, then the wdt will not run in stop mode. table 23. time-out period of wdt d1 do time-out of the internal rc osc time-out of the system clock 0 0 5 ms 128 sclk 0110 ms 1 256 sclk 1 1 0 20 ms 512 sclk 1 1 80 ms 2048 sclk note: the default setting is 10 ms. note:
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 63 wdt time-out in stop mode wi ll not reset smr,smr2,pcon, wdtmr, p2m, p3m, ports 2 & 3 da ta registers, but will activate the t por delay. wdtmr register accessibility . the wdtmr register is access ible only during the first 60 internal system clock cycl es from the execution of the firs t instruction after power-on reset, watchdog reset or a stop mode recovery ( figure 33 and figure 34 ). after this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank f of the expanded register file at address location 0fh . clock free wdt reset . the wdt will enable the z8 to reset the i/0 pins whenever the wdt times out, even without a clock sour ce running on the xtal1 and xtal2 pins. wdtmr bit d4 must be 0 for the clock free wdt to work. the i/o pins will default to their default settings. figure 33. watchdog timer mode register write only note: wdtmr (f) 0f 00 01* d7 d6 d5 d4 d3 d2 d1 d0 wdt tap reserved (must be 0) * default setting after reset 10 11 5 ms 10 ms int rc osc 25 ms 80 ms 128 tpc 256 tpc external clock 512 tpc 2048 tpc 0 off 1 on* wdt during halt 0 off 1 on* wdt during stop 0 on-board rc* 1 xtal xtal1/int rc select for wdt
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 64 figure 34. resets and wdt auto reset voltage . an on-board voltage comparator checks that v cc is at the required level to ensure correct operation of th e device. reset is globally driven if v cc is below vlv ( figure 35 ). internal reset reset 4 clock filter clear clk 18 clock reset generator reset 5ms por clk 5ms 15ms 25ms 100ms wdt/por counter chain clr m u x wdt tap select internal rc osc + - 2v operating voltage det. v dd v lv wdt from stop mode recovery source stop delay select (smr) wdt select (wdtmr) clk source select (wdtmr) xtal
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 65 figure 35. typical v lv voltage vs. temperature 3.5 3.3 3.1 2.8 2.7 2.5 2.3 -60 -40 -20 0 20 40 60 80 100 120 140 v cc (volts) temperature (c) 3.7
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 66 z8 control register diagrams ordering information figure 36. port configuration register (pcon) (write only) pcon (fh) 00h 0 p34, p37 standard output* 1 p34, p37 comparator output* d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 port 1 open-drain 1 port 1 push-pull active* ? 0 port 0 open-drain 1 port 0 push-pull active* 0 port 1 low emi 1 port 1 standard* ? 0 port 2 low emi 1 port 2 standard* 0 port 3 low emi 1 port 3 standard* 0 low emi 1 standard low emi character * default setting after reset ? must be set to ?1? for z86e33/733/e34 0 port 0 low emi 1 port 0 standard* ?
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 67 figure 37. stop mode recovery register (write only except bit d7, which is read only) smr (fh) 0b 0 off** 1 on d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 sclk/tclk = xtal/2* 1 sclk/tclk = xtal external clock divide-by-2 000 por only and/or external reset* 001 p30 stop-mode recovery source 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 0 off 1 on stop delay 0 low* 1 high stop recovery level 0 por* 1 stop recovery stop flag (read only) note: note used in conjunction with smr2 source * default setting after reset ** default setting after r eset and stop-mode recovery
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 68 figure 38. watchdog timer mode register (write only) figure 39. stop mode recovery register2 (write only) wdtmr (f) 0f 00 01* d7 d6 d5 d4 d3 d2 d1 d0 wdt tap reserved (must be 0) * default setting after reset 10 11 5 ms 10 ms int rc osc 20 ms 80 ms 128 tpc 256 tpc external clock 512 tpc 2048 tpc 0 off 1 on* wdt during halt 0 off 1 on* wdt during stop 0 on-board rc* 1 xtal xtal1/int rc select for wdt smr (0f) dh 00 por only* 01 and p20, p21, p22, p23 d7 d6 d5 d4 d3 d2 d1 d0 stop-mode recovery source 2 note: not used in conjunction with smr source 10 and p20, p21, p22, p23, p24, p25, p26, p27 reserved (must be 0)
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 69 figure 40. reserved figure 41. timer mode register (f1 h : read/write) r240 d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) r241 timer 0 no function 1 load t0 0 disable t 0 count 1 enable t 0 count 0 no function 1 load t 1 0 disable t 1 count 1 enable t 1 count t in modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) t out modes d7 d6 d5 d4 d3 d2 d1 d0 00 not used 01 t0 out 10 t1 out 11 internal clock out default after reset = 00h
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 70 figure 42. counter/timer 1 register (f2 h : read/write) figure 43. prescaler 1 register (f3 h : write only) figure 44. counter/timer 0 register (f4 h : read/write) r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 t 1 invalid value (when written) (range 1-258 decimal 01-00 hex) t 1 current value (when read) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 = t 1 single pass 1 = t 1 modulo n prescaler modulo (range: 1-64 decimal 01-00 hex) clock source 1 = t 1 internal 0 = t 1 external timing input (t in ) mode *default after reset t 0 initial value (when written) (range: 1-256 decimal r244 t0 d7 d6 d5 d4 d3 d2 d1 d0 01-00 hex) t 0 current value (when read)
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 71 figure 45. prescaler 0 register (f5 h : write only) figure 46. port 2 mode register (f6 h : write only) r245 pre0 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 = t 1 single pass 1 = t 1 modulo n prescaler modulo (range: 1-64 decimal 01-00 hex) reserved (must be 0) p20 - p27 i/o definition 0 defines bit as output 1 defines bit as input r246 p2m d7 d6 d5 d4 d3 d2 d1 d0 * default after reset
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 72 figure 47. port 3 mode register (f7 h : write only) r247 p3m 0 port 2 pull-ups open drain 1 port 2 push-pull active d7 d6 d5 d4 d3 d2 d1 d0 0 p31, p32 digital mode 1 p31, p32 analog mode 0 p32 = input 1 p32 = dav0 /rdy0 p35 = output p35 = dav0 /rdy0 0 p33 = input p34 = output 01 p33 = input 10 p34 = dm 11 p33 = dav1 /rdy1 p34 = rdy0/dav0 0 p31 = input (t in ) p36 = output (t out ) 1 p31 = dav2 /rdy2 p36 = rdy2/dav2 0 p30 = input p37 = output reserved (must be 0) ? z86e33/733/e34 must be 00 default after reset = 00h ? ?
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 73 figure 48. port 0 and 1 mode register (f8 h : write only) r248 p01m d7 d6 d5 d4 d3 d2 d1 d0 p00 ? p03 mode 00 output 01 input stack selection 0 external 1 internal ?* p10-p17 mode 00 byte output ? 01 byte input* 10 ad7-ad0 11 high-impedance ad7-ad0, a15-a12, if selected as , ds , r/w , a11-a8, external memory timing 0 normal 1 extended 1x a11-a8 p04-p07 mode 00 output 01 input* 1x a15-a12 * default after reset reset condition = 0100 1101b for romless condition = 1011 0110b ? z86e33/733/e34 must be 00
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 74 figure 49. interrupt priority register (f9 h : write only) figure 50. interrupt request register (fa h : read/write) r249 ipr d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved reserved (must be 0) irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq0 = p32 input r250 irq d7 d6 d5 d4 d3 d2 d1 d0 inter edge irq1 = p33 input irq2 = p31 input irq3 = p30 input irq4 = t0 irq5 = t1 p31 p32 p31 p32 p31 p32 p31 p32 = 00 = 11 = 10 = 01 default after reset = 00h
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 75 figure 51. interrupt mask register (fb h : read/write) figure 52. flag register (fc h : read/write) 1 enables irq5 -irq0 r251 imr d7 d6 d5 d4 d3 d2 d1 d0 1 enables ram protect* (d0 = irq0) 1 enables interrupts * this option must be selected when rom code is submitted for rom masking, otherwise this control bit is disabled permanently r252 flags d7 d6 d5 d4 d3 d2 d1 d0 user flag f2 halt carry flag decimal adjust flag overflow flag sign flag zero flag carry flag user flag f1
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 76 figure 53. register pointer (fd h : read/write) figure 54. stack pointer high (fe h : read/write) figure 55. stack pointer low (ff h : read/write) expanded register file r253 rp d7 d6 d5 d4 d3 d2 d1 d0 working register pointer default after reset = 00h stack pointer upper r254 sph d7 d6 d5 d4 d3 d2 d1 d0 byte (sp8-sp15) ( z86e33/733/e34 ) 0 = 0 state 1 = 1 state ( z86e43/743/e44 ) default after reset = 00h stack pointer lower r254 spl d7 d6 d5 d4 d3 d2 d1 d0 byte (sp0-sp7) default after reset = 00h
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 77 package information figure 56. 40-pin dip package diagram figure 57. 44-pin lqfp package diagram
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 78 figure 58. 28-pin dip package diagram figure 59. 28-pin soic package diagram
ps022901-0508 electrical characteristics cmos z8 ? otp microcontrollers product specification 79 ordering information table 24.ordering information product speed (mhz) package type pin count z86e3312psc 12 pdip 28 z86e3312scc 12 soic 28 z86e3312psc 12 plcc 28 z86e3412pec 12 pdip 28 z86e3412psc 12 pdip 28 z86e3412ssc 12 soic 28 z86e3412vsc 12 plcc 28 z86e4312fsc 12 lqfp 44 z86e4312psc 12 pdip 40 z86e4312vsc 12 plcc 44 z86e4412fsc 12 lqfp 44 z86e4412pec 12 pdip 40 z86e4412psc 12 pdip 40 z86e4412vsc 12 plcc 44 z8673312psc 12 pdip 28 z8673312ssc 12 soic 28 z8673312vsc 12 plcc 28 z8674312fsc 12 lqfp 44 z8674312psc 12 pdip 40 z8674312vsc 12 plcc 44
ps022901-0508 customer support cmos z8 ? otp microcontrollers product specification 80 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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